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// IP VLNV: xilinx.com:ip:fifo_generator:13.2
// IP Revision: 5

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
adc_fifo your_instance_name (
  .rst(rst),                // input wire rst
  .wr_clk(wr_clk),          // input wire wr_clk
  .rd_clk(rd_clk),          // input wire rd_clk
  .din(din),                // input wire [127 : 0] din
  .wr_en(wr_en),            // input wire wr_en
  .rd_en(rd_en),            // input wire rd_en
  .dout(dout),              // output wire [127 : 0] dout
  .full(full),              // output wire full
  .empty(empty),            // output wire empty
  .prog_full(prog_full),    // output wire prog_full
  .prog_empty(prog_empty)  // output wire prog_empty
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file adc_fifo.v when simulating
// the core, adc_fifo. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.