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// IP VLNV: analog.com:user:jesd204_rx:1.0
// IP Revision: 1

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
jesd204_rx_0 your_instance_name (
  .clk(clk),                                                    // input wire clk
  .reset(reset),                                                // input wire reset
  .phy_data(phy_data),                                          // input wire [127 : 0] phy_data
  .phy_header(phy_header),                                      // input wire [7 : 0] phy_header
  .phy_charisk(phy_charisk),                                    // input wire [15 : 0] phy_charisk
  .phy_notintable(phy_notintable),                              // input wire [15 : 0] phy_notintable
  .phy_disperr(phy_disperr),                                    // input wire [15 : 0] phy_disperr
  .phy_block_sync(phy_block_sync),                              // input wire [3 : 0] phy_block_sync
  .sysref(sysref),                                              // input wire sysref
  .lmfc_edge(lmfc_edge),                                        // output wire lmfc_edge
  .lmfc_clk(lmfc_clk),                                          // output wire lmfc_clk
  .event_sysref_alignment_error(event_sysref_alignment_error),  // output wire event_sysref_alignment_error
  .event_sysref_edge(event_sysref_edge),                        // output wire event_sysref_edge
  .sync(sync),                                                  // output wire [0 : 0] sync
  .phy_en_char_align(phy_en_char_align),                        // output wire phy_en_char_align
  .rx_data(rx_data),                                            // output wire [127 : 0] rx_data
  .rx_valid(rx_valid),                                          // output wire rx_valid
  .rx_eof(rx_eof),                                              // output wire [3 : 0] rx_eof
  .rx_sof(rx_sof),                                              // output wire [3 : 0] rx_sof
  .cfg_lanes_disable(cfg_lanes_disable),                        // input wire [3 : 0] cfg_lanes_disable
  .cfg_links_disable(cfg_links_disable),                        // input wire [0 : 0] cfg_links_disable
  .cfg_beats_per_multiframe(cfg_beats_per_multiframe),          // input wire [7 : 0] cfg_beats_per_multiframe
  .cfg_octets_per_frame(cfg_octets_per_frame),                  // input wire [7 : 0] cfg_octets_per_frame
  .cfg_lmfc_offset(cfg_lmfc_offset),                            // input wire [7 : 0] cfg_lmfc_offset
  .cfg_sysref_disable(cfg_sysref_disable),                      // input wire cfg_sysref_disable
  .cfg_sysref_oneshot(cfg_sysref_oneshot),                      // input wire cfg_sysref_oneshot
  .cfg_buffer_early_release(cfg_buffer_early_release),          // input wire cfg_buffer_early_release
  .cfg_buffer_delay(cfg_buffer_delay),                          // input wire [7 : 0] cfg_buffer_delay
  .cfg_disable_char_replacement(cfg_disable_char_replacement),  // input wire cfg_disable_char_replacement
  .cfg_disable_scrambler(cfg_disable_scrambler),                // input wire cfg_disable_scrambler
  .ctrl_err_statistics_reset(ctrl_err_statistics_reset),        // input wire ctrl_err_statistics_reset
  .ctrl_err_statistics_mask(ctrl_err_statistics_mask),          // input wire [6 : 0] ctrl_err_statistics_mask
  .status_err_statistics_cnt(status_err_statistics_cnt),        // output wire [127 : 0] status_err_statistics_cnt
  .ilas_config_valid(ilas_config_valid),                        // output wire [3 : 0] ilas_config_valid
  .ilas_config_addr(ilas_config_addr),                          // output wire [7 : 0] ilas_config_addr
  .ilas_config_data(ilas_config_data),                          // output wire [127 : 0] ilas_config_data
  .status_ctrl_state(status_ctrl_state),                        // output wire [1 : 0] status_ctrl_state
  .status_lane_cgs_state(status_lane_cgs_state),                // output wire [7 : 0] status_lane_cgs_state
  .status_lane_ifs_ready(status_lane_ifs_ready),                // output wire [3 : 0] status_lane_ifs_ready
  .status_lane_latency(status_lane_latency),                    // output wire [55 : 0] status_lane_latency
  .status_lane_emb_state(status_lane_emb_state)                // output wire [11 : 0] status_lane_emb_state
);
// INST_TAG_END ------ End INSTANTIATION Template ---------