################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com ## Mon Dec 10 13:48:21 2012 ## Generated by MIG Version 1.8 ## ################################################################################################## ## File name : example_top.ucf ## Details : Constraints file ## FPGA Family: KINTEX7 ## FPGA Part: XC7K325T-FFG900 ## Speedgrade: -2 ## Design Entry: VERILOG ## Frequency: 800 MHz ## Time Period: 1250 ps ################################################################################################## ################################################################################################## ## Controller 0 ## Memory Device: DDR3_SDRAM->SODIMMs->MT8JTF12864HZ-1G6 ## Data Width: 64 ## Time Period: 1250 ## Data Mask: 1 ################################################################################################## NET "sys_clk_p" TNM_NET = TNM_sys_clk; TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 5 ns; NET "led[0]" LOC = "AB8" | IOSTANDARD = LVCMOS15 | DRIVE = "12" | SLEW = "SLOW" ; # Bank 33: GPIO_LED_0_LS NET "led[1]" LOC = "AA8" | IOSTANDARD = LVCMOS15 | DRIVE = "12" | SLEW = "SLOW" ; # Bank 33: GPIO_LED_1_LS NET "led[2]" LOC = "AC9" | IOSTANDARD = LVCMOS15 | DRIVE = "12" | SLEW = "SLOW" ; # Bank 33: GPIO_LED_2_LS NET "led[3]" LOC = "AB9" | IOSTANDARD = LVCMOS15 | DRIVE = "12" | SLEW = "SLOW" ; # Bank 33: GPIO_LED_3_LS ############## NET - IOSTANDARD ################## NET "ddr3_dq[0]" LOC = "AA15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L20P_T3_32 NET "ddr3_dq[1]" LOC = "AA16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L23N_T3_32 NET "ddr3_dq[2]" LOC = "AC14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L22P_T3_32 NET "ddr3_dq[3]" LOC = "AD14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L22N_T3_32 NET "ddr3_dq[4]" LOC = "AA17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L23P_T3_32 NET "ddr3_dq[5]" LOC = "AB15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L20N_T3_32 NET "ddr3_dq[6]" LOC = "AE15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L19P_T3_32 NET "ddr3_dq[7]" LOC = "Y15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L24N_T3_32 NET "ddr3_dq[8]" LOC = "AB19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L17P_T2_32 NET "ddr3_dq[9]" LOC = "AD16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_32 NET "ddr3_dq[10]" LOC = "AC19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L17N_T2_32 NET "ddr3_dq[11]" LOC = "AD17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_32 NET "ddr3_dq[12]" LOC = "AA18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L16P_T2_32 NET "ddr3_dq[13]" LOC = "AB18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L16N_T2_32 NET "ddr3_dq[14]" LOC = "AE18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_32 NET "ddr3_dq[15]" LOC = "AD18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_32 NET "ddr3_dq[16]" LOC = "AG19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L8P_T1_32 NET "ddr3_dq[17]" LOC = "AK19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L7N_T1_32 NET "ddr3_dq[18]" LOC = "AG18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_32 NET "ddr3_dq[19]" LOC = "AF18" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_32 NET "ddr3_dq[20]" LOC = "AH19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L8N_T1_32 NET "ddr3_dq[21]" LOC = "AJ19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L7P_T1_32 NET "ddr3_dq[22]" LOC = "AE19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L10N_T1_32 NET "ddr3_dq[23]" LOC = "AD19" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L10P_T1_32 NET "ddr3_dq[24]" LOC = "AK16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L1P_T0_32 NET "ddr3_dq[25]" LOC = "AJ17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L5N_T0_32 NET "ddr3_dq[26]" LOC = "AG15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L2P_T0_32 NET "ddr3_dq[27]" LOC = "AF15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L4P_T0_32 NET "ddr3_dq[28]" LOC = "AH17" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L5P_T0_32 NET "ddr3_dq[29]" LOC = "AG14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L4N_T0_32 NET "ddr3_dq[30]" LOC = "AH15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L2N_T0_32 NET "ddr3_dq[31]" LOC = "AK15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L1N_T0_32 NET "ddr3_dq[32]" LOC = "AK8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L23N_T3_34 NET "ddr3_dq[33]" LOC = "AK6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L22N_T3_34 NET "ddr3_dq[34]" LOC = "AG7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L20N_T3_34 NET "ddr3_dq[35]" LOC = "AF7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L20P_T3_34 NET "ddr3_dq[36]" LOC = "AF8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L19P_T3_34 NET "ddr3_dq[37]" LOC = "AK4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L24N_T3_34 NET "ddr3_dq[38]" LOC = "AJ8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L23P_T3_34 NET "ddr3_dq[39]" LOC = "AJ6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L22P_T3_34 NET "ddr3_dq[40]" LOC = "AH5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_34 NET "ddr3_dq[41]" LOC = "AH6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_34 NET "ddr3_dq[42]" LOC = "AJ2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L16N_T2_34 NET "ddr3_dq[43]" LOC = "AH2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L16P_T2_34 NET "ddr3_dq[44]" LOC = "AH4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_34 NET "ddr3_dq[45]" LOC = "AJ4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_34 NET "ddr3_dq[46]" LOC = "AK1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L17N_T2_34 NET "ddr3_dq[47]" LOC = "AJ1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L17P_T2_34 NET "ddr3_dq[48]" LOC = "AF1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L8N_T1_34 NET "ddr3_dq[49]" LOC = "AF2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L7N_T1_34 NET "ddr3_dq[50]" LOC = "AE4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L10P_T1_34 NET "ddr3_dq[51]" LOC = "AE3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L10N_T1_34 NET "ddr3_dq[52]" LOC = "AF3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L7P_T1_34 NET "ddr3_dq[53]" LOC = "AF5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L11N_T1_SRCC_34 NET "ddr3_dq[54]" LOC = "AE1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L8P_T1_34 NET "ddr3_dq[55]" LOC = "AE5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L11P_T1_SRCC_34 NET "ddr3_dq[56]" LOC = "AC1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L2N_T0_34 NET "ddr3_dq[57]" LOC = "AD3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L1N_T0_34 NET "ddr3_dq[58]" LOC = "AC4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L4N_T0_34 NET "ddr3_dq[59]" LOC = "AC5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L4P_T0_34 NET "ddr3_dq[60]" LOC = "AE6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L5N_T0_34 NET "ddr3_dq[61]" LOC = "AD6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L5P_T0_34 NET "ddr3_dq[62]" LOC = "AC2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L2P_T0_34 NET "ddr3_dq[63]" LOC = "AD4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L1P_T0_34 NET "ddr3_addr[13]" LOC = "AH11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L18P_T2_33 NET "ddr3_addr[12]" LOC = "AJ11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L18N_T2_33 NET "ddr3_addr[11]" LOC = "AE13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L19P_T3_33 NET "ddr3_addr[10]" LOC = "AF13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L19N_T3_VREF_33 NET "ddr3_addr[9]" LOC = "AK14" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L20P_T3_33 NET "ddr3_addr[8]" LOC = "AK13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L20N_T3_33 NET "ddr3_addr[7]" LOC = "AH14" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_33 NET "ddr3_addr[6]" LOC = "AJ14" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_33 NET "ddr3_addr[5]" LOC = "AJ13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L22P_T3_33 NET "ddr3_addr[4]" LOC = "AJ12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L22N_T3_33 NET "ddr3_addr[3]" LOC = "AF12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L23P_T3_33 NET "ddr3_addr[2]" LOC = "AG12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L23N_T3_33 NET "ddr3_addr[1]" LOC = "AG13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L24P_T3_33 NET "ddr3_addr[0]" LOC = "AH12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L24N_T3_33 NET "ddr3_ba[2]" LOC = "AK9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_33 NET "ddr3_ba[1]" LOC = "AG9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L16P_T2_33 NET "ddr3_ba[0]" LOC = "AH9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L16N_T2_33 NET "ddr3_ras_n" LOC = "AD9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L10P_T1_33 NET "ddr3_cas_n" LOC = "AC11" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_33 NET "ddr3_we_n" LOC = "AE9" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L10N_T1_33 NET "ddr3_reset_n" LOC = "AK3" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L18N_T2_34 NET "ddr3_cke[0]" LOC = "AF10" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_33 NET "ddr3_odt[0]" LOC = "AD8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L8P_T1_33 NET "ddr3_cs_n[0]" LOC = "AC12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_33 NET "ddr3_dm[0]" LOC = "Y16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L24P_T3_32 NET "ddr3_dm[1]" LOC = "AB17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L18P_T2_32 NET "ddr3_dm[2]" LOC = "AF17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_32 NET "ddr3_dm[3]" LOC = "AE16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L6P_T0_32 NET "ddr3_dm[4]" LOC = "AK5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L24P_T3_34 NET "ddr3_dm[5]" LOC = "AJ3" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L18P_T2_34 NET "ddr3_dm[6]" LOC = "AF6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L12P_T1_MRCC_34 NET "ddr3_dm[7]" LOC = "AC7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L6P_T0_34 NET "sys_clk_p" LOC = "AD12" | IOSTANDARD = LVDS | VCCAUX_IO = DONTCARE ; # Pad function: IO_L12P_T1_MRCC_33 NET "sys_clk_n" LOC = "AD11" | IOSTANDARD = LVDS | VCCAUX_IO = DONTCARE ; # Pad function: IO_L12N_T1_MRCC_33 NET "sys_rst" LOC = "AB12" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = DONTCARE ; # Bank: 33 - Byte: T0 NET "ddr3_dqs_p[0]" LOC = "AC16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_32 NET "ddr3_dqs_n[0]" LOC = "AC15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_32 NET "ddr3_dqs_p[1]" LOC = "Y19" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_32 NET "ddr3_dqs_n[1]" LOC = "Y18" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_32 NET "ddr3_dqs_p[2]" LOC = "AJ18" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_32 NET "ddr3_dqs_n[2]" LOC = "AK18" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_32 NET "ddr3_dqs_p[3]" LOC = "AH16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_32 NET "ddr3_dqs_n[3]" LOC = "AJ16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_32 NET "ddr3_dqs_p[4]" LOC = "AH7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L21P_T3_DQS_34 NET "ddr3_dqs_n[4]" LOC = "AJ7" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L21N_T3_DQS_34 NET "ddr3_dqs_p[5]" LOC = "AG2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_34 NET "ddr3_dqs_n[5]" LOC = "AH1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_34 NET "ddr3_dqs_p[6]" LOC = "AG4" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L9P_T1_DQS_34 NET "ddr3_dqs_n[6]" LOC = "AG3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L9N_T1_DQS_34 NET "ddr3_dqs_p[7]" LOC = "AD2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_34 NET "ddr3_dqs_n[7]" LOC = "AD1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_34 NET "ddr3_ck_p[0]" LOC = "AG10" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_33 NET "ddr3_ck_n[0]" LOC = "AH10" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_33 INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y3; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y2; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y1; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y0; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y4; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y3; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y2; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y1; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y0; ## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6; ## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5; ## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y4; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y11; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y10; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y9; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y3; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y2; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y1; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y0; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y4; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y3; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y2; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y1; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y0; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y11; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y10; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y9; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y0; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y0; INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y43; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y31; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y19; INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y7; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y143; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y131; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y119; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y107; INST "*/u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1; INST "*/u_ddr3_infrastructure/mmcm_i" LOC=MMCME2_ADV_X1Y1; NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK"; INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE"; INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES"; TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 1250 ps; TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6; INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC"; TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY; ## Add for KC705: CONFIG DCI_CASCADE = "33 32 34";